Errata Corrections

2.4 Capacitors (DC)

Another useful equation is rise time. Rise time is defined as the time it takes to change from 10% of the final voltage to 90% of the final voltage. Rise time is approximately 2.2 times the time constant.

2.7 Capacitors (AC) / RC Filter

Plot equation: y=20*log(x) ? x=10(y/20)
when y= -3dB ? x=10(-3/20)
x=0.707 (70.7% of the input voltage)
when y= -20dB ? x=10(-20/20)
x=0.1 (10% of the input voltage)

3.5 FETs (Field Effect Transistors)

Drain voltages are rarely higher than source voltages. When the drain voltage exceeds the source voltage by approximately 0.6V (a diode forward voltage drop), the current flows backwards through the FET. Inserting a diode in series with the FET drain eliminates this problem (Figure 3.5 5).

   Figure 3.5-5<\em>
4.1 Comparators

   Figure 4.1-5
4.13 Voltage Supervisors

The Intersil ISL88002IE29Z-T and the Analog Devices ADM803SAKS detect when the voltage is below 2.92V. When this occurs, their output is 0V. This output is connected to a micro reset input. The 0V resets the micro.
5.12 SPI Serial Communication

Serial communication is access to one bit at a time.

SPI (Serial Peripheral Interface) is a standard serial communication protocol. It is comprised of one master and one, or more, slaves. The data is an MSB format.

A master outputs SpiClk (clock), SpiMoSi (master out slave in), and CS (chip select). A slave outputs SpiMiSo (master in slave out).
5.13 I2C Serial Communication

In Figure 5.13-2, the slave address is 0x2D, the data address is 0x4B, and the data is 0x1C. There could be additional bytes sent after the 0x1C.
5.14 RS-232 / RS-485 Serial Communication

For odd parity, the number of "1" bits, including the parity bit must be an odd number. In Figure 5.14-3 the parity bit is "1" for 0x03 (00000011b), and the parity bit is "0" for 0x64 (01100100b).


   Figure 5.14-3